Specifications

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I/O & Memory Maps
This appendix defines the I/O address map, memory chip selections, and memory
map for the EPC-30.
I/O Map
The EPC-30 uses both internal and external I/O mapped peripherals. Some
of the external devices require the use of a chip select while others perform
the address decode themselves.
Chip Select Device Address Range
(Hex)
Wait
States
Data
Width
Internal PIC 0 0020-0021 - -
Internal Address Cfg. Reg. 0022-0023 - -
Internal Timers 0-2 0040-0043 - -
GCS1# Keybrd/Mouse Ctrl. 0060, 0064 15d* 8
GCS2# RTC & Ext. CMOS 0070-0071 15d* 8
Internal Port 92 0092 - -
Internal PIC 1 00A0-00A1 - -
GCS4# IDE CS0 01F0-01F7 8/15d* 8/16*
Internal COMB 02E8-02FF - -
CL-GD6245 VGA Controller 03B0-03DF, 46E8 - 8/16 (2)
CL-PD6710 PC Card Controller 03E0-03E1 15d* 8/16 (2)
GCS3# IDE CS1 03F6-03F7 15d* 8
Internal COM1 03F8-03FF - -
Internal Chip Cfg. F400-F85F - -
Internal LPT Data F860-F864 - -
Internal LPT Ctrl./Stat. F870-F874 - -
Internal Chip Cfg. F875-F8FF - -
Table A-1. EPC-30 System I/O Map.
* Default cycles are 15 wait states for 8-bit and eight wait states for 16-bit.
Memory Chip Selects
Chip
Select
Device Address Range
(Hex)
Wait
States
Data
Width
Memory
Speed (ns)