Specifications

EPC-5A Hardware & Software Reference Manual
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Module Status/Control Register (8156h)
DONE AS DS0 DS1 1 1 (res.) 1
This register contains miscellaneous status and control bits.
DONE This read-only bit is 0 whenever the EPC-5A has a VMEbus access
outstanding. It is used for determining when a pipelined VMEbus write is
complete.
AS This read-only bit is 1 whenever the VMEbus AS (address strobe) signal is
asserted. It may be used for bus monitoring.
DS0 This read-only bit is 1 whenever the VMEbus DS0 (data strobe) signal is as-
serted. It may be used for bus monitoring.
DS1 This read-only bit is 1 whenever the VMEbus DS1 (data strobe) signal is as-
serted. It may be used for bus monitoring.
(res.) This bit should always be set (1).
The EPC-3 contains two additional bits in this register - ENMI and DEAD - for
breaking deadlock situations on its dual-port DRAM. These situations cannot exist in
the EPC-5A so the signals are not implemented.
VME Interrupt Generator Register (815Fh)
11111 INTERRUPT-OUT
This register is used to assert one of the VMEbus interrupt signals. If the
INTERRUPT-OUT bits are zero, no interrupt line is asserted by the EPC-5A. If the
lower three bits are set to 001, VMEbus IRQ1 is asserted. If set to 010, VMEbus
IRQ2 is asserted, and so on. If and when an interrupt acknowledge cycle is sent to the
EPC-5A, the INTERRUPT-OUT bits are cleared.
You can also deassert a previously asserted interrupt by writing 0 into the register.