Specifications

EPC-5A Hardware & Software Reference Manual
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VME Modifier Register (8151h)
VME WA23-22 BORD IACK AM5 AM4 AM2 AM1
This register is also used when the EPC-5A makes an access through its VME
memory window to the VMEbus. Bits 7 and 6 provide VME address bits A23 and
A22, respectively. Bits 3-0 define the value placed on the associated VMEbus
address-modifier lines. Register bits are not defined for the VMEbus address-
modifier AM3 and AM0 lines since, for all defined address-modifier values in the
VMEbus specification, AM3 is 1 and AM0 is the inverse of AM1. Therefore these
two bit values are generated by hardware. Note that because AM3 and AM0 are
hardware generated, the EPC-5A does not support user-defined address-modifiers.
BORD Byte order. This bit controls the ordering of data bytes for D16 and D32
VMEbus accesses. If 0, the bytes are transmitted in little endian (Intel)
order; if 1, byte-swapping hardware transmits the bytes in big endian
(Motorola) order. Refer to the previous section in this chapter on byte
ordering.
IACK This bit, when set, is used to define the VMEbus access as an interrupt
acknowledge cycle. The interrupt being acknowledged must be encoded by
software as a value on VME address lines A1-A3.
VME Interrupt State Register (8152h)
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR
This read-only register defines the state of the VMEbus and message interrupts.
IRQx If clear (0), the associated VMEbus interrupt line is asserted.
MSGR If clear (0), a message interrupt is being signaled. MSGR is clear if both bits
RRDY and WRDY in the response register are clear.