Specifications

EPC-5A Hardware & Software Reference Manual

Page 72

If A32 and SLE are set, the value in port 8147 defines the base address of the

EPC-5A’s memory in the VMEbus A32 address space. This register can hold the

values 18 - 1F, which correspond to the base addresses 18000000h - 1F000000h.

If A32 is clear and SLE is set, the two low-order bits of SLAVE BASE define the

base address of the EPC-5A’s memory in A24 as follows: 00 - 000000h, 01 - 400000h,

10 - 800000h, 11 - C00000h.

Protocol Register (8148h & 8149h)

11111111 Lower

01011111 Upper

This read-only register is defined by the VXIbus specification. In VXI systems, it de-

fines the EPC-5A as being a servant and commander, having no signal register, being

a bus master, and not providing fast handshake mode.

Response Register (814Ah & 814Bh)

LOCK 1 ABMH 1 1 ULA Lower

00001RRDY WRDY 1 Upper

With the exception of LOCK, this register is defined by the VXIbus specification.

It contains control bits associated with the message registers.

LOCK If set, the message register can be locked for the sending of a message.

If clear, the message register has been locked.

ABMH This bit is cleared when the message high register is read or written. It

serves as a location monitor for determining whether a message is 16 or 32

bits in length.

ULA Unique logical address. This determines the base of the registers in the

VMEbus A16 space. 0 denotes FE00h, 1 denotes FE40, 2 denotes FE80h,

3 denotes FEC0h, 4 denotes FF00h, 5 denotes FF40h, 6 denotes FF80h,

and 7 denotes FFC0h.

RRDY Read ready. As defined by VXI, a 1 denotes that the message registers

contain outgoing data to be read by another device. RRDY is cleared when

the message low register is read.