Specifications

EPC-5A Hardware & Software Reference Manual
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A32 If set (1), the EPC-5A’s DRAM is mapped into the VMEbus A32 address
space. If clear, the DRAM is mapped into the A24 address space. This read-
only bit is influenced by the value stored in the SLAVE-SIZE field of the
next register.
Device Type Register (8142h & 8143h)
11000100 Lower
0 Slave Size 11111 Upper
This register adheres to the VXIbus specification. Only bit 6 is writeable. Bit 5 is
automatically set to match bit 6. If bit 6 is set, the value of the register is 7Fh and the
A32 bit in the previous register is 1. This denotes that the EPC-5A responds to a 16
MB range in the A32 space.
If bit 6 is clear, the value of the register is 1Fh and the A32 bit in the previous register
is 0. This denotes that the EPC-5A responds to a 4 MB range in the A24 space.
The remaining ROM bits define the EPC-5A as having a model code of 4036.
Status/Control Register (8144h & 8145h)
SRIE RELM ARBPRI READY PASS NOSF RSTP Lower
SLE MODID SYSR SYSF ARBM 1 1 1 Upper
This register adheres to the VXIbus specification and also contains EPC-5A specific
bits.
SRIE SYSRESET input enable. If set, assertion of VME SYSRESET generates a
reset of the EPC-5A. One use of this bit is having EPC-5A software reset
other VME devices (via bit SYSR) without resetting the EPC-5A.
RELM Bus release mode. If set, the bus release mode is ROR (release on request);
otherwise it is the VXI RONR “fair requester” mode (request on no
request). Altering this bit via the VME-mapped location of this register has
no effect.