Specifications

Chapter 6: The VMEbus Interface
Page 63
Slave Accesses from the VMEbus
When SLE (Slave Enable) in the status/control register (8145h) is set, the EPC-5A’s
dual-ported memory will respond to accesses from other VMEbus masters.
All types of VME accesses (reads, writes, and read-modify-writes of all lengths) are
supported, except for block transfer cycles. The EPC-5A responds to supervisory,
non-privileged, program, or data access modes.
The amount of memory that will be dual-ported is limited to the first (lowest address)
4 MB in A24 space or all available memory in A32 space. In both cases, the slave
memory’s local (PC) address starts at Segment 0000, Offset 0000. This, of course,
means that it is possible to overwrite the memory space occupied by the operating
system. As such, care must be taken in writing to the EPC-5A’s memory.
When such an access is fielded by the EPC-5A, the EPC-5A’s A24 or A32 base
address is effectively subtracted from the VMEbus address value, and the result is
treated as if the access came from the 486.
However, note the following:
1. Any access that maps to local addresses 000A0000h - 000BFFFFh,
000D0000h 000EFFFFh, to addresses mapped to the EPC-5A’s EXM
expansion interface, and to addresses beyond the extent of the installed
DRAM cause the EPC-5A to respond with BERR (bus error).
2. Write accesses to write-protected DRAM terminate normally (DTACK
response), but with no effect on the DRAM.
Enabling of the EPC-5A as a slave and specification of the address space (A24 or
A32) and the base address is controlled by the registers discussed in the following
section, Registers Specific to the EPC-5A. The easiest way to set up these registers is
to do so via the BIOS setup screen.