Specifications

EPC-5A Hardware & Software Reference Manual
Page 58
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When configured as the Slot-1 controller, the EPC-5A detects and terminates data
transfer bus timeouts. Once it sees either the
DS0 or DS1 lines asserted, a counter is
started. If the counter expires before both
DS0 and DS1 are deasserted, the
EPC-5A asserts the VMEbus
BERR signal until both data strobes are deasserted. The
duration of the VMEbus timeout counter is 100-120 µsecs. When the EPC-5A is
configured as the slot-1 controller, this timeout cannot be disabled and the duration
cannot be changed.
Although the EPC-5A provides the required timeout function for data transfer time-
out, it does not provide the optional bus grant timeout. If another master has been
granted permission to use the data bus but does not access (or relinquish) the data bus,
the bus will be “hung” indefinitely.
Concepts
Memory Map
VMEbus accesses are available by mapping a 64K segment of the VMEbus through
the 0E0000h -0EFFFFh window or by direct mapping above 256 MB. The following
summarizes the source of the VMEbus address lines for accesses through the VME
memory window.
A32
31 2423 2221 1615 0
From
port
8150
From
port
8151
From
port
8130
From
486 address
bits 15-0
A24
23 2221 1615 0
From
port
8151
From
port
8130
From
486 address
bits 15-0
A16
15 0
From
486 address
bits 15-0
Figure 6-1. Source of VMEbus Address Lines (Via VME memory window).