Specifications

Chapter 9: Troubleshooting & Error Messages
Page 103
99
Phoenix NuBIOS Checkpoints
The Phoenix NuBIOS writes a number of checkpoints to I/O port 80h just
before they are executed. Note that the execution order of the POST tests
generally follows the order listed in the tables below, but not exactly. In addition,
some checkpoints are not implemented, but the entire table is presented here for
completeness.
Beep Code Post Code Checkpoint Description
02h Verify Real Mode
04h Get CPU type
06h Initialize system hardware
08h Initialize system controller registers with initial
POST values
09h Set in POST flag
0Ah Initialize CPU registers
0Bh Enable CPU cache
0Ch Initialize cache to initial POST values
0Eh Initialize I/O
0Fh Initialize localbus IDE
11h Load alternate registers with initial POST values
12h Jump to UserPatch0
14h Initialize keyboard controller
1-2-2-3 16h BIOS ROM checksum
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset programmable interrupt controller
1-3-1-1 20h Test DRAM refresh
1-3-1-3 22h Test 8742 keyboard controller
24h Set ES segment to register to 4GB
28h Autosize DRAM
2Ah Clear 512KB base RAM
1-3-4-1 2Ch Test 512KB base address lines
1-3-4-3 2Eh Test low byte of 512KB base memory
1-4-1-1 30h Test high byte of 512KB base memory
32h Test CPU bus-clock frequency
34h Test CMOS RAM
35h Initialize alternate system controller registers
36h Warmstart shutdown entry point
37h Reinitialize the system controller