Specifications

Theory of Operation

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Watchdog timer

A watchdog timer function is included to provide either an NMI or a RESET signal

to the CPU in the event that software loses control of the system.

A register is present that enables or disables the watchdog timer function and allows

the selection of different timeout periods. The register returns the value FF when

read. It is defined as follows:

Watchdog Register 0x388:

D7 - D4 D3-D2 D1 D0

Timeout Length Unused Watchdog NMI enable Watchdog RESET enable

If the timeout length bits are set to 0, the watchdog timeout is set to 125 mS.

Otherwise, the timeout length bits define a four bit number which adds additional

time to the period (in steps of 125 mS) up to a maximum of 2 seconds. Times are

approximate; the actual timing is done off the ISA-bus refresh signal using a long

counter.

If the watchdog enable bits are set to 0, the watchdog function is available only on

the TIMEOUT pin of the miscellaneous connector. If either bit is set to 1, watchdog

time-outs will be enabled on the corresponding line to the CPU (NMI or RESET).

The watchdog signals (TIMEOUT and/or NMI and/or RESET) will be asserted if the

specified time interval elapses with no read or write from the watchdog register.

Once asserted, the signals remain asserted until the counter is reset by accessing this

Upon power-on reset and all AT-bus resets, this register is initialized to 0x00.

ISA-bus

Connection is made to the ISA-bus through a standard PC/AT-style card edge

connector. This connector includes two sections; one is a 31-position connector, and

the second an 18-position connector. Each position has one contact on each side of

the board. These card edge connectors are designed, positioned and connected per

the ISA-bus specification and are gold plated, 30 micro inch [0.76 micron]

minimum, over nickel.