Specifications
Theory of Operation
Page 31
3 3
SRAM disk subsystem
Two 128Kx8 SRAM devices may be factory-installed on the EPC-33/34. This
SRAM is not located in the processor's memory address space; it is accessed
indirectly through I/O reads and writes. Single byte I/O writes to 0x380-0x382 are
saved in latches that set up the lower, middle, and high address bits that drive the
SRAM’s address lines.
I/O reads/writes to 0x384 access the SRAM data at the address stored in the latches.
Each read or write from the data port also increments the address in the latches to
allow efficient reading or writing of sequences of bytes in the SRAM. These latches
are initialized to 0x00 at power-up and will be cleared by any AT-bus reset.
In order to use the SRAM as a disk device, you must first format it, using the
SRAMFMT.EXE utility, then load the SRAMDISK.SYS device driver during the
boot process.
Flash disk subsystem
The EPC-33/34 can contain an optional Flash disk up to 8 MBytes in size, using a
module and a full read/write Flash file software system licensed from M-Systems.
The system can also be booted from the Flash disk.
+12V (a maximum of 150ma is required) must be supplied via the power connector
or the ISA-bus (or PC/104 sockets) to allow erasing and writing the Flash disk
device.
The interface to the Flash disk is implemented through a memory window in the
ISA-bus memory space at E000:0. This memory window is programmed using a
range comparator function of the PicoPower PC/AT chipset. The upper address bits
which select pages within the 4MB Flash disk are provided by two registers at I/O
port 0x389-A. These registers provide the upper twelve bits of the Flash address. (In
a 4MB system, only 10 of these bits are used.)
The register at 0x38B is used to select the size of the window used to access the
Flash. The bits in this register select the source of the A15-A12 address bits sent to
the Flash memory. If the bits in 0x38B are ‘0’ then the ISA-bus address bits are
used. If the bits in 0x38B are ‘1’ the lower bits of 0x389 are used. The window size
must also be programmed into the chipset to provide the appropriate address decode.