Specifications

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3. Theory of Operation
This chapter contains information about the following:
• EPC-33/34 processor
• Memory
• BIOS Flash EPROM
• Super VGA/Flat Panel controller subsystem
• SRAM Disk subsystem
• Flash Disk subsystem
• Ethernet port
• Watchdog timer
• ISA-bus
• Miscellaneous functions
• Resetting the EPC
• Power Requirements
• Peripheral interfaces
• IDE interface
Processor
The EPC-33 uses the 50 MHz Intel486 DX2 central processing unit (CPU). The
EPC-34 uses the 100 MHz IntelDX4 CPU. Both CPUs are in a 208-pin PQFP
package, and both contain an integrated math coprocessor. Note that this is not a
socketed part, and therefore is not field-upgradable.
The board design uses the PicoPower chip set to interface the 80486 to the AT-bus.
The chip set is packaged in two 176-pin TQFPs and supports mixed voltage designs
(5V/3.3V).