Specifications

Appendix C: Registers

For compatibility with other EPCs, when writing to this register assign 0 to reserved bit 5

and 1 to reserved bit 3.

VME Interrupt State Register (8152h)

This read-only register defines the state of the VMEbus and message interrupts.

IRQx If clear (0), the associated VMEbus interrupt line is asserted.

MSGR If clear (0), a message interrupt is being signalled. MSGR is clear if both of bits

RRDY and WRDY in the response register are clear.

VME Interrupt Enable Register (8153h)

This is a mask of the interrupt conditions in the interrupt state register. A 1 denotes that the

corresponding interrupt is enabled. If any bit in this register is a 1 and the corresponding

bit in the interrupt state register is a 0, the EPC-6A IRQ10 interrupt is asserted. Software

may then examine the interrupt and event state registers to determine the cause.

VME Event State Register (8154h)

Similar to the interrupt state register, this register defines additional conditions that may

result in an IRQ10 interrupt. If the bit is 0, the condition is present.

WDT The EPC-6A’s watchdog timer’s period has expired.

ACFA VMEbus ACFAIL is asserted.

BERR An access from the EPC-6A to the VMEbus was terminated with a BERR (bus

error).

SYSF VMEbus SYSFAIL is asserted.

All bits are read-only except BERR. BERR is a sticky bit that is cleared whenever an

access from the EPC-6A is terminated by a bus error, and remains clear (0) unless changed

by software (by writing any value to this register).

VME Event Enable Register (8155h)

This is a mask of the interrupt conditions in the event state register. A 1 denotes that the

corresponding event is enabled as an interrupt. If any bit in this register is a 1 and the

corresponding bit in the event state register is a 0, the EPC-6A IRQ10 interrupt is asserted.

Software may then examine the interrupt and event state registers to determine the cause.

VME Interrupt State Reg

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR

VME Interrupt Enable Reg

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR

VME Event State Register

1111WDTACFABERRSYSF

VME Event Enable Register

1111WDTACFABERRSYSF