Specifications

EPC-6A Hardware Reference
36
Phoenix NuBIOS Checkpoints
The Phoenix NuBIOS writes a number of checkpoints to I/O port 80h just before they are
executed. Note that the execution order of the POST tests generally follows the order
listed in the tables below, but not exactly.
Table 6-2. Phoenix NuBIOS Auxiliary Checkpoint Codes
05 DRAM initialization 1C Interrupt controller test
06 DRAM 0- and F-page test 1D Interrupt controller test
07 DRAM byte enable logic test 1E Battery level test
08 Copy ROM 1F CMOS checksum test
09 Copy ROM 20 Configuration byte initialization
0A Copy ROM 21 Size system memory
0B Copy ROM 22 System memory test
0C Copy ROM 23 Stuck interrupt test
0D Copy ROM 24 Stuck NMI (parity/IOCHK) bit test
0E Clear 8042 interface 25 Interrupt controller test
0F Reset 8042 interface 26 Size extended memory
10 PC hardware initialization 27 Extended memory test
11 Video interface initialization 28 VME interface test
12 Timer test 29 VXI register test
13 CMOS shutdown test 2A COM1 serial port test
14 DMA test 2B COM2 serial port test
15 DMA test 2C Cache test
16 DMA page registers test
17 does not occur
Beep code Post code Checkpoint description
02h Verify Real Mode
04h Get CPU type
06h Initialize system hardware
08h Initialize system controller registers with initial
POST values
09h Set in POST flag
0Ah Initialize CPU registers
0Bh Enable CPU cache
0Ch Initialize cache to initial POST values
0Eh Initialize I/O
0Fh Initialize localbus IDE
11h Load alternate registers with initial POST values
12h Jump to UserPatch0
14h Initialize keyboard controller
1-2-2-3 16h BIOS ROM checksum
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset Programmable Interrupt Controller
1-3-1-1 20h Test DRAM refresh
Code Description Code Description