Specifications

Chapter 5: Theory of Operation
31
Interrupts
The following table shows interrupt assignment.
Table 5-1. Interrupts
Watchdog Timer
EPC-6A contains a continually running timer having a period of approximately either 8
seconds or 250 milliseconds (software selectable). The watchdog timer event is generated
whenever the period expires. This event may be enabled as a source of the IRQ10 interrupt
or as a complete reset. The timer is reset to its maximum value by an I/O write to the
module status/control register.
EXMbus
The EXM bus, an I/O expansion bus, is provided on a connector to allow the user to insert
one EXMbus module. The EXMbus is very similar to the PC/AT ISA I/O bus. In addition,
it contains a signal -EXMID used for dynamic recognition and configuration of EXMs.
EXMs respond to one or more I/O addresses in the range 100h–107h only when their
–EXMID line is asserted. EXMs are required to return a unique EXM-type identification
byte in response to a read from I/O address 100h. Since the EPC-6A has only a single
EXM slot, its –EXMID line is wired as asserted.
Although IRQ11 is on the EXMbus, IRQ11 is also used by the reset/abort toggle switch
and is driven by a totem-pole driver that has no tristate. Thus the IRQ11 interruptIRQ11
interrupt is not available to EXM modules.
Further information on the EXMbus, its connectors, and standards for building EXMs is
available upon request.
Interrupt Source
NMI
DRAM parity error, EXMbus I/O channel check
IRQ0 Timer (connected to R400 internal 8254 count 0 out)
IRQ1 Keyboard controller (R400 internal)
IRQ2 Cascade interrupt input
IRQ3 COM2 serial port
IRQ4 COM1 serial port
IRQ5 unassigned
IRQ6 unassigned/floppy disk
IRQ7 unassigned
IRQ8 Real-Time clock
IRQ9 unassigned
IRQ10 VME interrupt/event
IRQ11 front-panel toggle switch
IRQ12 not available
IRQ13 coprocessor (FERR)
IRQ14 unassigned/IDE
IRQ15 unassigned