Specifications

EPC-8 Hardware Reference

5 5

5-12

Bits 1 and 2 of the Module Status/Control register (0x815D) are cleared by a ‘‘warm

reset’’. This keeps the watchdog timer from expiring on a ‘‘warm reset’’ that is not

initiated from a source other than a watchdog timeout. ENSYSO (bit 6 of 0x815D)

also has to be cleared by the BIOS in response to warm resets to keep from losing the

watchdog timeout bit while setting the BTOE bit (the VME Bus Timeout Enable bit).

The watchdog timer is enabled by setting the WDTR bit (bit 3 of register 815D).

Note that a watchdog hardware reset results in a "warm" hardware reset. An I/O read

to address 815D resets the counter.

To program the watchdog timer, follow these steps:

1. Determine if you want the watchdog timer to reset the EPC-8 or signal a

watchdog timer event using IRQ 10. Use bit 3 in the Module

Status/Control Register (815D). If set to 1, the EPC resets. If set to 0, the

event is signaled.

2. Determine if you want the system to 1) halt or 2) continue rebooting on

the watchdog timer event. From the EPC-8 BIOS Advanced Menu,

choose which option you prefer enabled.

3. Set the speed of your watchdog timer. Options are 8.2 seconds, 128 mS,

or 1.02 seconds. Use bits 1 and 2 of register 815D. Bit 1 is the slow timer

and bit 2 is the fast timer. When used in conjunction, the settings are as

follows:

01 = 8.2 seconds

10 = 128 mS

11 = 1.02 seconds

The timer is reset to its maximum value by an I/O read of the module status/control

counter just prior to enabling the interrupt bit in register 8155. This will inhibit a

spurious timer event from occurring just after enabling the timer.

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