Specifications

EPC-8 Hardware Reference

5 5

5-2

Read-Modify-Write Operations

VMEbus RMW (read-modify-write) cycles can be performed through use of the

LOCK instruction prefix with certain instructions. All of these instructions perform a

read followed by a write. When such a read occurs that is mapped to the VMEbus,

the EPC-8 treats it as the start of a VME RMW cycle. The next VME access from the

CPU is treated as the write that terminates the RMW cycle. Keep in mind that

accesses that cross a 32-bit boundary are actually performed as two accesses. For this

reason, RMW accesses that cross a 32-bit boundary will not behave as expected.

Also, many compilers will not actually generate a 32-bit access. Instead, two 16-bit

accesses are generated. This can also cause an 32-bit RMW cycle to terminate

prematurely with unexpected results.

Setting the VMEbus Access Bit

Before any VMEbus accesses can occur, the VMEbus access bit must be set. The

EPC-8 provides two separate VMEbus access bits corresponding to the two access

methods described above. Both of these access bits are part of the configuration

the bit (0) disables accesses. Bit 0 is used to enable direct VMEbus accesses above

256 MB. Bit 1 enables E-page accesses. In some cases, the programmer may wish to

enable both access methods. However, if bit 1 is set (E-page accesses enabled), then

the 64K of upper memory located from E000:0000 to EFFF:FFFF will not be

available for use as system memory. If the application program is going to enable the

E-page window, care must be taken to ensure that the Operating System will not be

using this address space. Otherwise a memory conflict will occur that will cause the

Operating System to fail at some point.

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