Specifications

EPC-8 Hardware Reference
4 4
4-16
• Drives the 16 MHz SYSCLK signal
• Starts the IACK bus grant daisy chain.
• Provides Bus time-out function
When configured as the Slot-1 controller, the EPC-8 detects and terminates data
transfer bus timeouts. Once it sees either the
DS0 or DS1 lines asserted, a counter is
started. If the counter expires before both DS0 and DS1 are deasserted, the
EPC-8 asserts the VMEbus BERR signal until both data strobes are deasserted. The
duration of the VMEbus timeout counter is approximately 100-120 µsecs.
When the EPC-8 is configured as the slot-1 controller, this timeout cannot be disabled
and the duration cannot be changed.
VMEbus Access
VMEbus accesses are available either by mapping a 64 Kbytes segment of the
VMEbus through the 0E0000-0EFFFF "E page" window or by direct mapping above
256 Mbytes.
Byte Ordering
There are two fundamentally different ways of storing numerical values in byte loca-
tions in memory:
• Little endian, characteristic of Intel microprocessors, where the
least-significant data byte (LSB) is stored in the lowest byte address
Address + 3 Address + 2 Address + 1 Address
Byte 3 Byte 2 Byte 1 Byte 0
MSB
LSB
• Big endian, characteristic of Motorola microprocessors and the VMEbus
environment in general, where the most-significant data byte (MSB) is
stored in the lowest byte address
Address + 3 Address + 2 Address + 1 Address
Byte 3 Byte 2 Byte 1 Byte 0
LSB MSB
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