Specifications

EPC-8 Hardware Reference
4 4
4-14
The EPC-8's reaction to SYSRESET* being asserted on the VME bus depends upon
whether the SRIE bit (SYSRESET Input Enable, bit 7 of the Status/Control register)
is set or clear. When SRIE is asserted (set), the assertion of SYSRESET* results in
the same "warm" hardware reset that a watchdog timer reset causes. When SRIE is
not asserted, the EPC-8 responds to the assertion of SYSRESET* by placing the EPC-
8 into a state almost identical to the Soft Reset state. The only difference between the
two states is that the PASS bit (bit 2 of Status/Control register) is not cleared by the
assertion of SYSRESET* (as long as SRIE is 0 - to avoid a warm reset), but the PASS
bit is cleared by the assertion the SRST bit.
Signal Register FIFO
To spell out the operation of the Signal Register FIFO and associated control bits, the
operations are explained in algorithmic fashion. SIG, FSIG and LSIG are fields in the
Response register. The signal FIFO, called SRFIFO henceforth, is a two-element
array with indexes.
A write to VPR from the VXI is a write to the signal register (and FIFO), and does the
following:
if (SIG && (FSIG != LSIG)) { /* FIFO full */
assert BERR;
}
else {
if (SIG) LSIG = !LSIG;
SRFIFO[LSIG] = data_bus;
...SIG = 1
}
A read from SRFL returns the low-order byte of SRFIFO(FSIG). In all cases of
accesses to SRFL and SRFH, if SIG = 0 (empty FIFO), the result is an access to
SRFIFO(0). A read from SRFH returns the high-order byte of SRFIFO(FSIG), and
does the following:
if (FSIG == LSIG) {SIG = LSIG = FSIG = 0}
else FSIG = !FSIG;
Writes to SRFL and SRFH (I/O address 0x8148,0x8149) are identical to reads except
for the direction of the data flow (e.g., writing to SRFH alters the high-order byte of
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