Specifications

Theory of Operation

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A ‘‘cold’’ or hardware reset of the EPC-8 (not a keyboard CTRL+ALT+DEL reset)

clears all of the register bits to 0, except for RELM, ARBM, and ARBPRI, which may

be in an undefined state. (All bits, however, are cleared by a power-on reset.)

However, this may not be apparent because the BIOS initialization sequence then

reinitializes values in these register fields, largely as a result of the non-volatile

configuration information specified in the setup screen.

VME/VXI Soft RESET state and SYSRESET

"Soft Reset" is a capability that allows another VME master to disable the EPC-8's

connection to the VME bus, without interrupting (or resetting) the 486 processor on

the EPC-8.

The Soft Reset state is entered when the SRST bit is set. In this state the EPC-8

removes any asserted interrupts (clears the Interrupt Generator register, disables its

VME master logic, asserts both the VMER and BERR sticky bits in the VME Event

State register, disables watchdog timer resets and interrupts, and clears the PASS bit.

SYSFAIL will also be asserted if the NOSF (SYSFAIL inhibit) bit is clear. The

Slot-1 arbitration and control logic and the bus timeout function, if it is enabled, is

unaffected by the SRST bit. Software on the EPC-8 can detect that another board has

set the EPC-8 into Soft Reset state by several different methods:

(1) Enable the interrupt events associated with either the VMER bit or BERR bit.

(2) After each VME master access poll the BERR bit. If this bit is set either a true bus

timeout occurred (VMER will not be asserted in this case) or the Soft Reset state has

been entered (both VMER and the BERR bits are asserted).

The Soft Reset state can be exited by a push-button reset, a power-on reset, by simply

writing a 0 to the SRST bit, or by the assertion of SYSRESET when the SRIE bit is

also set. When SRST is cleared by writing the bit to 0, the VMER and BERR bits

should also be cleared by writing to the VME Event State register, VME master

accesses will again be enabled (if they were enabled prior to SRST being asserted),

and the watchdog functions, that were enabled prior to SRST being asserted, resume

(with the counter starting in the cleared state).

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