Specifications

EPC-8 Hardware Reference
4 4
4-12
Power-On
Reset
Power
Low
< 3.0 V
Power
Heading
Lower 3-
4.5 V
Front-
Panel
Reset
Button
Ctrl-
Alt-Del
VME
bus
SysReset
Line
Asserted
Watch
dog Timer
‘‘Cold’’
reset
‘‘Cold’’
reset
‘‘Warm
reset
‘‘Warm’’
reset
Soft
ware
reset
‘‘Warm’’
reset
‘‘Warm’’
reset
POST
runs
POST
runs
POST
runs
POST
runs
No
POST
POST runs POST
runs
80C486,
82C486,
all VXI
registers
reset
80C486,
82C486,
all VXI
registers
reset
80C486,
82C486,
most VXI
registers
reset
80C486,
82C486,
most VXI
registers
reset
80C486,
82C486,
most VXI
registers
reset
80C486,
82C486,
most VXI
registers
reset
bits 4-7 of
8102 not
reset;
bits1,2,4
& 6 of
815D not
reset
bits 4-7 of
8102 not
reset;
bits1,2,4
& 6 of
815D not
reset
bits 4-7 of
8102 not
reset;
bits1,2,4 &
6 of 815D
not reset
bits 4-7 of
8102 not
reset;
bits1,2,4
& 6 of
815D not
reset
AT.
RESET
generated
AT.
RESET
generated
AT.
RESET
generated
AT.
RESET
generated
No AT.
RESET
AT.
RESET
generated
AT.
RESET
generated
SYS
RESET*
generated
SYS
RESET*
generated
SYS
RESET*
not
generated
unless bit
6 of 815D
is set
SYS
RESET*
not
generated
unless bit
6 of 815D
is set
No
SYS
RESET
*
SYS
RESET*
not
generated
unless bit 6
of 815D is
set
SYS
RESET*
not
generated
unless bit
6 of 815D
is set
SYS
FAIL
asserted
until
watch
dog timer
is reset
Table 4-1. Reset Conditions.
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