Specifications

EPC-8 Hardware Reference

4 4

4-8

Watchdog Timer

The watchdog timer is a binary counter which, upon overflow, will signal a watchdog

timer event. The counter will cause a watchdog event after approximately 125 mS, 1

second or 8 seconds (depending on the value of FWDT and SWDT, bits 2 and 1 in

An I/O read to address 815D resets the counter. If WDTR (bit 3 of register 815D) is

set, the following occurs in response to a timeout event:

WDT (bit 3 of register 8154) is set. A local ‘‘warm’’ hardware reset occurs

(SYSRESET* is not driven unless ENSYSO bit has been set, bit 6 of 0x815D). Bits 1,

2, and 3 of register 815D are cleared to prevent the watchdog timer from expiring on a

warm reset that is initiated from a source othe than a watchdog timeout. ENSYSO (bit

6 of 815D) is cleared by the BIOS in response to warm resets to keep from losing the

watchdog timeout bit while setting the BTOE bit. VME SYSFAIL* is also asserted.

When exiting a hardware reset condition, the BIOS can check the WDT bit. If this bit

is set (0), then a watchdog timeout caused the hardware reset (as opposed to

SYSRESET or power-on reset). Then depending on the value of a setup option the

BIOS will either HALT the CPU or allow the boot process to continue. At this point,

software may deassert the VME SYSFAIL* condition by reading the register at

0x815D.

Note that a watchdog hardware reset results in a "warm" hardware reset. A warm

hardware reset clears all register bits except for the upper four bits of the

Configuration register (these control Slot-1 arbitration functions) and bits 4 and 6 of

the Module Status/Control registers (these control bus timeout function and watchdog

timer functions). A warm reset does clear WDTR (bit 3 of the Module Status/Control

SYSFAIL will continue to be driven until the WDT bit is cleared by either reading

the Module Status/Control Register or by a power-on reset.

If WDTR is clear, WDT mask (bit 3 of register 8155) enables an interrupt if a timeout

event occurs (SYSFAIL is not driven). The clock is disabled to the counter if the

interrupt is pending and not serviced. Service of the interrupt is signaled to the

counter by reading register 815D. This will reset the counter value and resume

counting. The interrupt is signaled on IRQ10. The timer event also clears WDT bit in

the BES register (bit 3 of register 8154).

Application software that utilizes this timer should take care to reset the counter just

prior to enabling the interrupt bit in register 8155. This will inhibit a spurious timer

event from occurring just after enabling the timer.

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