Specifications

Product Description

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VMEbus

The VMEbus implementation provides a complete bus interface with enhancements

for multiprocessor environments. This is described in three sections covering the

system controller functions, the VMEbus master interface, and VMEbus extended

System controller functions

A single hardware configuration jumper allows the EPC-8 to provide full VME slot-1

arbitration functions. When enabled, the functions provided include priority and

round-robin bus arbitration, IACK and bus grant daisy-chain driving, SYSRESET and

SYSCLK generation and bus time-out detection. ROR (release-on-request) or a fair-

requester, RONR (release-on-no-request) bus release mechanism is software

selectable.

VMEbus master interface

The VMEbus master interface provides a full 32-bit data path to the 16, 24, and 32-bit

address spaces of the VMEbus. The bus interface is designed with a minimum

number of state registers, which maximizes performance in a multitasking or interrupt

driven environment.

Programmable hardware byte-swapping is provided for ease of communication with

other processor architectures that may share the VMEbus. All the VMEbus address

spaces can be addressed from both protected-mode and real-mode operating systems.

The EPC-8 can generate or respond to all 7 standard VMEbus interrupts, and can also

receive the VMEbus signals ACFail, BERR, and Sysfail as interrupts. When it is used

to generate interrupts, it implements 16-bit IACK cycles.

VMEbus extended register set

As an extension to the VMEbus interface, the EPC-8 implements the set of VXIbus

(IEEE 1155-1992) standard multiprocessor support registers in the A16 space.

These registers provide a set of standard identification, status, control and

communication functions that are useful in multiprocessor environments. They allow

dynamic system configuration by providing for board identification, and provide well-

defined multi-processor communications channels and protocols.

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