Specifications

EPC-8 Hardware Reference
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o Phoenix BIOS with RadiSys enhancements to support the additional on-board
features and VMEbus environment.
Additional features (some optional) include:
o SVGA interface. This local-bus interface is based on the Cirrus GD54xx chipset,
with 512 Kbytes of video RAM providing local bus graphics performance and
non-interlaced resolutions to 1024 x 768, with 16 colors. The standard 15-pin
connector for this port is enhanced with a programmable output on pin 15, which
is not connected on a standard VGA interface.
o 10-Base-T Ethernet interface. The interface is based on the National
Semiconductor AT/LANTIC chip set, which provides emulation of Western
Digital WD8013, Novell NE2000 and NE2000+ Ethernet controllers. Interface
configuration (Emulation mode and address/interrupt control) is software
controlled; a DOS-based application is provided to perform this operation.
o A second modified RS-422/485 PC-compatible serial port. This interface is
implemented with RS-422/485 transmit and receive buffers. CTS, RTS, DSR and
DTR are buffered to RS-422 levels. The Transmit lines are controlled by the RTS
signal, providing RS-485 multidrop support.
o A watchdog timer. This device can be configured to generate a VMEbus
SYSFAIL signal and reset the processor. The processor can be configured to
reboot or halt. The timer is implemented as a software-retriggerable one-shot,
with a programmable reset interval ranging from 125 mS to 8000 mS.
o The ability to boot from VMEbus memory or resident Flash memory.
o (optional) 128 Kbytes of battery-backed memory-mapped static RAM.
o (optional) 2 Mbytes of flash-EPROM based non-volatile memory. This memory
can be protected against accidental overwriting by removing a shorting jumper.
Software is available to support this in the DOS/Windows environment. This
memory can also be configured as a bootable disk.
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