Specifications

Registers
F F
F-15
Offset from
ULA
Upper byte Lower byte
0 ID (8141) ID (8140)
2 Device type (8143) Device type (8142)
4 Status/control (8145) Status/control (8144)
6 Reserved (8147) Reserved (8146)
8 Protocol/Signal (8149) Protocol/Signal (8148)
A Response (814B) Response (814A)
C Message high (814D) Message high (814C)
E Message low(814F) Message low(814E)
2A Alternate Response Alternate Response
The registers occupy the first 16 bytes of the 64-byte space, but DTACK (BERR in
the case of an LWORD or Signal FIFO overflow access) will be signaled for accesses
within the entire 64 byte region. Note that the registers may only be written by using
the lower 16 addresses. Writes between address offsets 16-64 have no effect. For
reads, the registers are aliased every 16 bytes (e.g. a read at offset 0x10,0x20,0x30
will return the data in the ID register). The lone exception to this rule occurs when
accessing the Alternate Response register.
Reads and writes of the registers from VME and as I/O ports have identical results and
effects except where noted in the register descriptions above.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com