Specifications

EPC-8 Hardware Reference
F F
F-14
SWDT Slow watchdog timer. FWDT and SWDT produce the following timeout
values: 00 - disables events from the watchdog timer , 01 - 8.2 s, 10 - 128ms,
11 - 1.02 s.
A read of the module status/control register also has a side effect of resetting the
watchdog timer. Therefore, if you are using the watchdog timer, the intention is that
you are required to read this register within the defined period of the timer to prevent
its generating an interrupt.
VMEbus Mapped Registers
The EPC-8 maps a standard set of VXI configuration registers onto the VMEbus A16
space and thus accessible by other VMEbus modules. These registers are 16-bit
registers occupying 64 bytes of A16 space at a base address defined by the EPC-8's
logical address.
The base address is
11aa aaaa aa00 0000
where aaaaa aaaa is the value of the ULA field in the response register at I/O port
815C.
The VME-mapped registers are a subset of those defined previously as I/O ports in the
EPC-8. The registers are dual-ported in that they are accessible both from VME and
from within the EPC-8 as ports in its I/O space. The VME mapped registers are
defined below. Please note that the odd addresses from VME port will access the
lower byte (registers addressed by even PC I/O addresses). The registers may be
accessed using D08 and/or D16 accesses from the VME port.
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