Specifications

Registers

F F

F-13

Bit 7 of register 8158 is read-only and returns the value of the slot1 jumper setting . If

the slot 1 shunt is installed (slot1 operation), then 0 is returned. If the slot1 shunt is

not installed, then 1 is returned.

Unique Logical Address Register (815C)

ULA

This register contains the EPC-8's ULA. The ULA contents are used to map the

EPC8's register set into VME A16 space as described below in the VMEbus Mapped

Registers section. The ULA is changed by writing into this register or into the ID

Module Status/Control Register (815D)

DONE ENSYSO

1 BTOE WDTR FWDT SWDT 1

This register contains the following miscellaneous status and control bits: Only bit 3,

WDTR, is cleared by a warm reset. All bits of this register, except for the read-only

DONE status bit, are cleared by a power-on reset.

DONE This read-only bit is 0 whenever the EPC-8 has a VMEbus access

outstanding. It is used for determining when a pipelined VMEbus write is

complete.

ENSYSO This register bit, if set, will cause SYSRESET* to be asserted when any

“warm” hardware reset (push-button reset, watchdog reset, SYSRESET*

input, or low +5V resets) occurs on the EPC8. This bit is cleared during

power-on reset only. Warm hardware resets do not clear it.

BTOE Bus timeout enable. Enables the slot-0 bus timeout timer. This is used by

the BIOS.

WDTR Watchdog timer reset enable. If 1, expiration of the watchdog timer

generates a reset of the EPC-8. If 0, only the WDT event is signaled. A read

of the module status register should be performed before enabling the

watchdog timer reset. This clears the watchdog counter to zero so that a PC

reset does not occur immediately after enabling the watchdog timer reset.

FWDT Fast watchdog timer.

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