Specifications

EPC-8 Hardware Reference

F F

F-12

BERR This bit is cleared (asserted low) when an access from the EPC-8 to the

VMEbus is terminated with a BERR (bus error). It is also held clear when

the SRST bit is set. This bit may be deasserted by writing a "1" (provided

SRST is not asserted) into this bit position.

SYSF VMEbus SYSFAIL is asserted.

WDT Watchdog timer expired

VMER A SYSRESET or soft reset has occurred. This bit is held clear while

SYSRESET is asserted or the SRST bit is asserted. This bit may be

deasserted by writing a "1" into it once the reset conditions have been

removed.

SIGR Signal register FIFO is not empty.

All bits are read-only except BERR and VMER. BERR is a sticky bit that is cleared

whenever an access from the EPC-8 is terminated by a bus error or is held clear, and

remains clear (0) unless changed by software (by writing any value to this register).

VME Event Enable Register (8155)

VMER SIGR WDT ACFA BERR SYSF

The low-order six bits are a mask of the interrupt conditions in the event state register.

A 1 denotes that the corresponding event is enabled as an interrupt. If any bit in this

IRQ10 interrupt is asserted. Software may then examine the interrupt and event state

registers to determine the cause.

VME Interrupt Generator Register (8158)

SLOT1* 1 1 1 1 INTERRUPT-OUT

This register is used to assert one of the VMEbus interrupt signals. If the INTER-

RUPT-OUT bits are zero, no interrupt line is asserted by the EPC-8. If lower three

bits are set to 001, VMEbus IRQ1 is asserted. If set to 010, VMEbus IRQ2 is

asserted, and so on. If and when an interrupt acknowledge cycle is sent to the EPC-8,

the INTERRUPT-OUT bits are cleared. You can also deassert a previously asserted

interrupt by writing 0 into the register. Finally, this register is cleared whenever

SYSRESET* is asserted or when the SRST (soft reset) bit is asserted.

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