Specifications

Registers
F F
F-11
BORD Byte order. This bit controls the ordering of data bytes for D16 and D32
VMEbus accesses. If 0, the bytes are transmitted in little endian (Intel)
order; if 1, byte-swapping hardware transmits the bytes in big endian
(Motorola) order. Refer to the previous section in this chapter on byte
ordering.
IACK This bit, when set, is used to define the VMEbus access as an interrupt ac-
knowledge cycle. The interrupt being acknowledged must be encoded by
software as a value on VME address lines A1-A3.
VME Interrupt State Register (8152)
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR
This read-only register defines the state of the VMEbus and message interrupts.
IRQx If clear (0), the associated VMEbus interrupt line is asserted.
MSGR If clear (0), a message interrupt is being signaled. MSGR is clear if both bits
RRDY and WRDY in the response register are clear.
VME Interrupt Enable Register (8153)
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR
This is a mask of the interrupt conditions in the interrupt state register. A 1 denotes
that the corresponding interrupt is enabled. If any bit in this register is a 1 and the
corresponding bit in the interrupt state register is a 0, the EPC-8 IRQ10 interrupt is as-
serted. Software may then examine the interrupt and event state registers to determine
the cause.
VME Event State Register (8154)
1 1 VMER SIGR WDT ACFA BERR SYSF
Similar to the interrupt state register, this register defines additional conditions that
may result in an IRQ10 interrupt. If the bit is 0, the condition is present. All bits are
read-only except for the VMER and BERR signals.
ACFA VMEbus ACFAIL is asserted.
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