Specifications
EPC-8 Hardware Reference
F F
F-8
A write to the signal register is a happening of some significance for the EPC8, since
it potentially asserts an EPC interrupt, shuffles a signal-register FIFO, and may return
BERR if the FIFO is already full. For these reasons, the full semantics of writing to
the signal register are discussed separately in a later section.
Response Register (814A & 814B)
R RRIEN 1 SIG MCLK WRCP FSIG LSIG
Lower
0 1 DOR DIR ERR RRDY WRDY 1
Upper
This register contains some VXI-defined state bits associated with message handling,
and several EPC-8 dependent bits. All of these bits may read/written (except where
noted below) from both the PC and VME ports. Some of this bits may also be cleared
by certain hardware events as described below.
DOR RAM bit available to software for VXI communication protocols.
DIR RAM bit available to software for VXI communication protocols.
ERR RAM bit available to software for VXI communication protocols.
RRDY Read ready. A 1 denotes that the message registers contain outgoing data to
be read by another device. RRDY is cleared when the message low register
is read.
WRDY Write ready. If set, the message registers are armed for an incoming mes-
sage. When a write occurs into the message-low register, WRDY is cleared
and the MSGR interrupt condition is asserted.
R RAM bit available to software.
RRIEN This EPC-8 specific bit is used to enable RRDY interrupt signaling. When
clear (hardware reset state), only the deassertion of WRDY will cause the
MSGR interrupt to be asserted. When set, the "OR" of the deasserted
RRDY, WRDY bits is used to assert the interrupt. This bit would normally
only be set for protocols that require multiple reply data to be sent in
response to a single command.
SIG If this EPC-8 specific bit is 0, the signal register FIFO is empty. This bit is
read-only.
MLCK This EPC-8 specific bit is used for synchronization of messages from
multiple senders, something not provided for in the VXI specification. If 1,
the message register can be locked for the sending of a message. If 0, the
message register has been locked.
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