Specifications

Registers
F F
F-7
SYSR SYSRESET. The EPC-8 asserts the VME SYSRESET line while this bit
is 1. When using this bit, it is the software's responsibility to ensure that
the VME-specified minimum assertion time of SYSRESET is met. This bit
may be read/written from the PC port, but is read-only from the VME port.
R A read/write bit that is available for software use (e.g. SURM).
RESDET This bit is cleared by a hardware reset. Once this bit is written to “1” from
the PC-port (read-only from the VME port) it can only be set to zero by a
hardware reset. This bit is used by the firmware to determine if a software
or hardware reset is in progress and it set to “1” before any OS or
application is invoked.
Reserved (8146 & 8147)
These registers are reserved and return all ones if read.
Protocol Register/Signal FIFO (8148 & 8149)
1 1 1 1 1 1 1 1 Lower
0 0 0 1 1 1 1 1 Upper
A read of this register from either the PC or VME ports reads the ROM constants
stored in the protocol register. A write from either the PC or VME port writes the
signal register.
The protocol register (the read value) defines the EPC-8 as being a servant and
commander, having a signal register, being a bus master and an interrupter, not
providing the shared-memory protocol, and not providing fast handshake mode.
When written from the VXIbus, this register is the signal register. The value written
enters the signal FIFO (two deep) or returns a bus error (BERR) if the FIFO is already
full.
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