Specifications

EPC-8 Hardware Reference
F F
F-6
This register adheres to the VXIbus specification and also contains EPC-8 specific
bits.
SRIE SYSRESET input enable. If set, assertion of VME SYSRESET generates
a reset of the EPC-8. One use of this bit is having EPC-8 software reset
other VME devices (via bit SYSR) without resetting the EPC-8. This bit
may be read/written from the PC port, but is read-only from the VME port.
SYSCLK SYSCLK status bit. Only PC port writes to this register have the effect of
clearing this bit. The bit is then set if four rising edges of the SYSCLK
signal are detected. This bit is intended to be used to detect that SYSCLK
is being generated on the backplane.
READY This is a RAM bit defined by the VXI specification. In a VXIbus software
environment, if READY=1 and PASS=1, the EPC-8 is ready to accept
VXI-defined messages. This bit is read-only from the VME port and may
be read/written from the PC port. This bit is also held clear while the
SRST bit is asserted. When deasserting SRST via an I/O write to this
register, a second write will be required to be able to reassert the READY
bit since the READY bit is held in reset until just after the first write
completes.
PASS If set (1), the EPC-8 has completed its self test successfully. If this bit is
clear, the Test LED on the EPC-8 front panel is lit. This bit is read-only
from the VME port and may be read/written from the PC port. This bit is
also held clear while the SRST bit is asserted. When deasserting SRST via
an I/O write to this register, a second write will be required to be able to
reassert the PASS bit since the PASS bit is held in reset until just after the
first write completes.
NOSF SYSFAIL inhibit. If set, the EPC-8 will not assert the VMEbus SYSFAIL
line due to the PASS bit being cleared. If the PASS bit is clear and this bit
is clear, then SYSFAIL will be asserted. SYSFAIL is also asserted when a
Watchdog timeout reset occurs, independent of the setting of this bit. This
bit may be read/written from both the VME and PC ports.
SRST Soft Reset. Setting this bit places the EPC8 into the soft reset state. This
bit may be read/written from both the VME and PC ports.
MODID This read-only bit is connected to pin 30 in row A of the VMEbus P2 con-
nector. If clear (0), it denotes that the pin is being pulled high. (This is
used in VXI systems for module identification.) Note, this bit is defined
but not implemented in the EPC-8 and will always return a value of 1. If
future versions of the product need this capability it can be provided by
installing a resistor.
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