Specifications

EPC-8 Hardware Reference
F F
F-4
VME-32 VME 32-bit enable. If set (1), this bit enables VME accesses through
the 32-bit addressing mechanism. When clear (0), this mechanism is
disabled. This bit is automatically set by the BusManager software
when using EPConnect. Please note the VMER bit (bit 5 of the VME
Event State register), if asserted, will also disable this function, but
does not clear the VME-32 bit.
VME-E VME E-page enable. If set (1), this bit enables VME accesses through
the DOS "E page". When clear (0), the E page is available for DOS
use. This bit is automatically set by the BusManager software when
using EPConnect. Please note the VMER bit (bit 5 of the VME
Event State register), if asserted, will also disable this function, but
does not clear the VME-32 bit.
VGA VGA enable. If set (1), this bit enables the VGA controller. This bit
powers up clear and if the BIOS detects another VGA controller in the
system it is not set. Once this bit is set via write of "1" to this register
only a hardware reset can clear it.
GPO VGA General Purpose output control. This inversion of this bit is tied
to pin 15 of the VGA connector through a 150 ohm resistor.
ARBPRI Arbitration priority. This defines the level at which the EPC-8 will ar-
bitrate for the VMEbus. 11 means 3, 10 means 2, 01 means 1, 00
means 0.
RELM Bus release mode. If set, the bus release mode is ROR (release on
request); otherwise it is the VXI RONR "fair requester" mode (request
on no request).
ARBM Arbitration mode. This bit is pertinent only if the EPC-8 is jumpered
to be the slot 1 controller. If set, the EPC-8 is a priority arbiter; other-
wise it is a round-robin arbiter.
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