Specifications

Registers
F F
F-3
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR
8152
VME Interrupt State Register
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8153
VME Interrupt Enable Register
1 1 VMER SIGR WDT ACFA BERR SYSF 8154
VME Event State Register
1 1 VMER SIGR WDT ACFA BERR SYSF 8155
VME Event Enable Register
SLOT1* 1 1 1 1 INTERRUPT-OUT 8158
Interrupt Generator Register
ULA 815C
Unique Logical Address Register
DONE ENSYSO 1 BTOE WDTR FWDT SWDT 1 815D
Module Status/Control Register
RAM 815E
Signal FIFO, lower (read-only address)
RAM 815F
Signal FIFO, upper (read-only address)
Where a bit position has been described by a 0 or 1, the bit is a ROM bit, and writing
to it has no effect. Unless otherwise noted below, all registers and bit values are
readable and writeable.
Configuration (8102)
ARBPRI RELM ARBM GPO VGA VME-E VME-32
This register controls enables of the VGA controller and the VMEbus. Only the lower
four bits in this register are cleared by an "AT reset" (that is, when the RESET button
is pushed or WDT reset occurs or SYSRESET occurs). All eight bits are cleared by a
power-on reset.
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