Specifications

75
B
Interrupts
The following table shows interrupt assignments for the EPC-3305.
Table B-1. Interrupts
Interrupt Description
IRQ0 System timer (internal PIIX4E connection)
IRQ1 Keyboard controller
IRQ2 Cascade interrupt input (internal PIIX4E connection)
IRQ3 COM 1
IRQ4 COM 2
IRQ5 Unused
IRQ6 Floppy (if enabled)
IRQ7 CompactPCI Hot Swap interrupt (if enabled)
IRQ8 Real time clock
IRQ9 Unused
IRQ10 Hot Swap event
IRQ11 Watchdog first stage timeout
IRQ12 PS/2 mouse (if enabled)
IRQ13 Numeric coprocessor ~FERR (internal PIIX4E connection)
IRQ14 Primary IDE
IRQ15 Unused
NMI PIIX4E when ~SERR or ~IOCHK is asserted (software controlled)
SMI Power management
PIRQA PMC A, PMC B, CompactPCI ~INTA if receive CompactPCI
interrupts is enabled
PIRQB Drawbridge, PMC A, PMC B, CompactPCI ~INTB if receive
CompactPCI interrupts is enabled
PIRQC ENET 1, PMC A, PMC B, CompactPCI ~INTC if receive
CompactPCI interrupts is enabled
PIRQD ENET 2, PMC A, PMC B, CompactPCI ~INTD if receive
CompactPCI interrupts is enabled
Note that PIRQ[A–D] correspond directly to the PCI interrupts INT[A–D].
The software may steer these interrupts to any of the 11 interrupts (IRQ[15,
14, 12–9, 7–3]) using the Interrupt Route Control register.