Specifications
EPC-3305 Hardware Reference
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next table defines the bit position to control these features. All bits are active high,
with the exception of the ENUM bit.
IRQ_7 Enables an interrupt on ENUM from the 21554 drawbridge or
CompactPCI backplane. If set to one, an interrupt occurs when ENUM
asserts.
IRQ_11 Enables IRQ 11 when the CPU ejector latch opens. If set to one, IRQ 11
asserts as long as the latch remains in the open position.
INIT Enables an INIT on a soft reset. If set to one, the INIT line to the
processor is strobed on a soft reset. You can use these values:
Disabled A reset source programmed to generate a soft reset does not
reset (INIT) the processor.
Enabled (POR default) Resets (INIT) the processor. Use this to
produce a timed interrupt with no processor reset.
IRQ_10 Enables IRQ_10 on a soft reset. If set to one, IRQ 10 asserts for 63 ms
before the INIT signal to the processor is strobed.
NMI Enables an NMI on a soft reset. If set to one, the NMI line asserts for
63 ms before the INIT signal to the processor is strobed.
CompactPCI features register
The CompactPCI Features register provides a means for software to read:
• CompactPCI geographic address
• CompactPCI SYSEN bit
• RTM present
This register allows software to route CompactPCI interrupts to the local processor.
Note that the CompactPCI backplanes rotate the interrupts from slot to slot. It is up
to software to de-rotate (if required) the source of the interrupts. Slot position can
be determined by reading the Geographical Address from the CPLD.
SYSEN The SYSEN signal from the CompactPCI backplane. This is an active low
signal. If zero it indicated that the CPU card is plugged into the System
Table 4-9. Local interrupt enables
R/W Index Default D7 D6 D5 D4 D3 D2 D1 D0
R/W 0x05 0x04 — IRQ7 — IRQ 11 — INIT IRQ 10 NMI
Plug the EPC-3305 into a system slot only if the system is specifically
designed around the EPC-3305 feature set. The EPC-3305 is not designed
as a system card.
Table 4-10. CompactPCI features register
R/W Index D7 D6 D5 D4 D3 D2 D1 D0
R (D5 R/W) 0x09 SYSEN #RTM _P INTS_ IN GA4 GA3 GA2 GA1 GA0