Specifications

EPC-3305 Hardware Reference
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(POR) value is zero, indication hard reset. A value of one causes that reset source to
generate a soft reset sequence.
FP_RST Selects one of these hard or soft reset attributes for the Front Panel reset
switch:
0 (zero) Hard reset.
1 Soft reset.
RTM_RST Selects one of these hard or soft reset attribute for the RTM reset switch:
0 (zero) Hard reset.
1 Soft reset.
WD_RST Selects one of these hard or soft reset attribute for the Watchdog timer:
0 (zero) Hard reset.
1 Soft reset.
The Reset Event register determines the source of the last reset.
FAIL_SOFT
Indicates that the soft reset attempt failed, and was therefore followed by
a hard reset.
POR Identifies the last reset as a Power on Reset, active high
FP Identifies the last reset as from the Front Panel Switch, active high
RTM Indicates that the last reset was from the RTM, active high
WD Indicates that the last reset was from the Watchdog timer, active high
Watchdog timer
The watchdog timer is a counter that can be programmed to time out and produce a
hard or soft reset. The timeout has six selections ranging from 0.5s to 4 minutes.
The type of reset generated is selected by the Reset Control Register, bit 0.
Application software can prevent the watchdog event from occurring by a dummy
write (data written is irrelevant) to the Kickdog Register.
Table 4-5. Reset control register
R/W Index Default D7 D6 D5 D4 D3 D2 D1 D0
R/W 0x05 0x00 ————FP_RST RTM_RST — WD_RST
Table 4-6. Reset event register
R/W Index Default D7 D6 D5 D4 D3 D2 D1 D0
R/W 0x04 0x20 FAIL_SOFT — POR — FP RTM cPCI WD