Specifications

Chapter 4: Theory of operation

Software must first write to the index register before reading or writing to the data

Reset controller

The EPC-3305 implements three types of resets: POR, Hard Reset, and Soft Reset.

A POR and Hard Reset are identical: all registers are set to their initial value (with

the exception of the Reset Event Register which retains the source of the hard reset).

A soft reset only resets the processor through an INIT. The INIT, in conjunction

with the BIOS, preserves memory contents on a soft reset.

There are two stages to a soft reset:

1. The CPU is issued an NMI or IRQ10 (if enabled) then, 62 ms after the NMI, an

INIT is issued to the CPU.

2. A timer starts in the CPLD. If the BIOS fails to write to the KickDog register

after four seconds during boot, the timer times out and produces a hard reset.

This prevents a hang condition if the soft reset fails.

The CPU board can also be reset individually by the host CPU through CompactPCI

configuration space.

Reset control

Each of the reset sources can be independently configured to generate a soft or a

hard reset. This attribute is controlled by the Assign Reset Type register. The default

Reset event

0x04 R Identifies reset source

Local interrupt

enables

0x05 R/W Enables/disables various interrupts

from the CPLD

Reset control 0x06 R/W Assigns Hard or Soft reset attribute

to various reset sources

Unused 0x07 N/A None

BIOS control 0x08 R/W Selects which BIOS banks are

active, enables/diables WP.

CompactPCI

features

0x09 R/ W bit-5 only CompactPCI geographical addres,

~SYSGEN, CompactPCI interrupt

route, RTM present.

Unused 0x0A–

0xFE

——

CPLD revision 0xFF R Indicates PLD revision

Table 4-4. CPLD indexes for function registers

Name

Index

value R/W Function