Specifications

EPC-3305 Hardware Reference
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The keyboard interrupt connects to IRQ1. If enabled, the mouse interrupt utilizes
IRQ12. The keyboard and mouse connectors are located on the RTM.
Special features
The EPC-3305 includes these features:
• Watchdog timer
• Three reset modes
• Software access to CompactPCI Geographical Address and ~SYSEN pin
• Interrupt routing to allow all CompactPCI interrupts to be routed to the local
PIIX4E
• Multiple BIOS flash pages
• Local interrupt on a Hot Swap event
The CPU board uses a CLPD to implement the unique features.
CPLD ISA interface
The CPLD provides an ISA interface to control feature parameters. The default
values of the CPLD registers shown are for a Power on Reset (POR).
The ISA interface uses an I/O address each for data, an index register, and the kick
watchdog bit. The base address is
0x0180 and is implemented with ~PCS1 of the
PIIX4. If ~PCS1 is asserted, data can be written into either register or read from the
data register. Note that the index register is write-only. The PIIX ~PCS1 is
configured by the BIOS to decode an I/O range from 0180 to 018F. The register
offsets are defined as follows:
Table 4-3. CPLD I/O ports
Name
Base
(Set by ~PCS1 in the PIIX) Default Function
Index 0x0185 0x00 Points to register inside CPLD for
reading or writing
Kickdog 0x0186 N/A Kicks watchdog to prevent a
watchdog timeout
Data 0x0187 0x00 Data to be read or written
Table 4-4. CPLD indexes for function registers
Name
Index
value R/W Function
Reserved 0x00 ——
Watchdog
control
0x01 R/W Kick watchdog, enable watchdog
Unused 0x02 N/A None
Front panel LED 0x03 — Controls R/G LED on front panel