Specifications

EPC-3305 Hardware Reference

panel. For the Ethernet channel routed to both the front panel and J5 there is an

auto detect circuit, which routes the signal to the appropriate RJ45. Once the auto-

detect circuit has routed the signal, only a loss of link can cause the auto-detect

circuit to re-activated.

The Ethernet controllers use PCI interrupts and REQ/GNT signals shown in Table

4-2. PCI Device Configuration. The 82559s have a standard PCI 2.1 compliant

configuration space allowing easy system identification and configuration.

The PHY enables direct connection to the network media using a 25 MHz, 25 ppm

crystal to derive its internal transmit digital clocks. In 100BASE-TX mode, the

analog subsection of the PHY does the following:

• Takes received analog data from the RD pair and converts it into a digital 125

Mbps stream, recovering both clock and data.

• Converts a digital 125 Mbps stream into the proper format and drive it through

the TD pair into the physical medium.

The 82559 defines a maximum distance of 25.4 mm between itself and the

associated magnetics and another 25.4 mm distance between the magnetics and the

RJ45.

Ejector handle switch

Two ejector handles with built-in switches are provided on the front panel of the

CPU Board. Releasing the ejector handles from the lock position to the eject

position sets a switch which is connected to the LID input of the PIIX4E. When

asserted, the LID input sets a bit in the general purpose status register (see the

PIIX4E datasheet for more details). Assertion of this bit can generate an SMI if this

response is enabled.

Battery

The 3.0V lithium battery supplied with the EPC-3305 and mounted on the CPU

board is a Renata CR2032 “coin cell” or equivalent. Should the battery fail, you

may obtain and install a replacement. For information about replacing the battery,

see Replacing the battery on page 8.

The battery powers the CMOS RAM and TOD clock when system power is not

present. If system power is present, the +5V voltage also powers the CMOS RAM

and TOD clock. This is done with the +3.3V isolation diodes, so that either the

The Intel specification for distance from the PHY to the magnetics must be

violated in this design since the magnetics reside on the RTM near the RJ45.

The BIOS does not enable the SMI feature. The OS/application software

must enable the SMI feature and have a SMI handler in place to respond to

this type of event.

Write down all CMOS setup parameters while the battery is still good, or save

them using the options available on the BIOS configuration’s CMOS Save

and Restore sub-menu.