Specifications

Chapter 4: Theory of operation

21554 to hide subsystem resources from the host processor and to resolve any

resource conflicts that may exist between the host and local subsystems.

The 21554 configuration space is divided into these parts:

• Primary interface configuration registers

• Secondary interface configuration registers

• Device-specific configuration registers

Both the primary and secondary interface configuration headers contain the 64-byte

Type 0 configuration header that corresponds to that interface. The device-specific

configuration registers are specific to the 21554, some of which apply to the

primary interface, others to the secondary interface, and some to other 21554

functions.

Both the primary and secondary interfaces support access to the 21554

configuration registers. The serial ROM attached to the 21554 can pre-load some

configuration parameters prior to initialization. This enables vendor-specific

configuration parameters to load into the 21554 configuration registers, replacing

default values specified by Intel. These vendor-specific parameters load before

configuration of the 21554 by the local and/or host processors. Pre-loadable

parameters include address mapping requirements, Class Code, Subsystem ID and

Subsystem Vendor ID, and others. During the preload operation, all accesses to the

21554 configuration registers receive a target retry.

CPU board reset on host command over CompactPCI

The CPU board may be reset by the System Slot CPU. This is achieved by having the

Host write to the Reset Control Register in the Drawbridge’s PCI configuration

space. The secondary reset out from the Drawbridge will force a hard reset of the

CPU board. There are two bits the host can use, bit-0 and bit-1. If it is desired to

hold the CPU board in rest the host should write a value of one to D8. The board

will then stay in reset until the host clears that bit. If it is desired to only reset the

board, the host should set D8 to a value of two. This will reset the board and is self

clearing, requiring no further action by the host.

(21554 PCI-to-PCI Bridge for Embedded Applications User’s Manual, page 7-39 )