Specifications

EPC-3305 Hardware Reference
50
• Extended bank: Contains 128 bytes used as general purpose RAM. Time,
calendar, and alarm can be represented in either binary or BCD format. The
format is determined by bit 2 of Control Register B. The hour is represented in
12- or 24-hour format, and the format is selected by bit 1 of Control Register B.
The RTC operates on a 32.768 kHz crystal and a separate battery.
The RTC also supports two lockable memory ranges. Configuration space allows
locking two 8 byte ranges to read and write accesses by setting specific bits. This
prevents unauthorized reading of passwords or other system security information.
Power management logic
The PIIX4E provides full support for the Advanced Configuration and Power
Interface (ACPI) Specification. For detailed information, see the 82371AB
PCI-to-ISA / IDE Xcelerator (PIIX4) specification available from Intel’s web page.
Intel 21154 PCI-PCI bridge
The 21554 performs PCI bridging functions for embedded and intelligent I/O
applications. The 21554 is a non-transparent PCI-to-PCI bridge that acts as a
gateway to an intelligent subsystem. The 21554 functions as a bridge between two
PCI processor domains, the host domain and the local domain. Special features of
the 21554 include:
• Support for independent primary and secondary PCI clocks
• Independent primary and secondary address spaces
• Address translation between the primary (host) and secondary (local) PCI
buses (domains).
The 21554 creates a configuration barrier between the two PCI domains. Standard
hierarchical PCI configuration methods using Type 1 configuration transactions
cannot be used to access the configuration space of devices on the opposite side of
the 21554. The 21554 uses a Type 0 configuration header, which presents the entire
subsystem as a single “device” to the host processor.
The 21554 forwards transactions between the primary and secondary PCI buses as
does a transparent PCI-to-PCI bridge. In contrast to a transparent PCI-to-PCI
bridge, however, the 21554 can translate the address of a forwarded transaction
from a system address to a local address, or vice versa. This mechanism allows the
When changing the format, the time registers must be reinitialized to the
corresponding data format.
The RTC (as supported by the BIOS) is Y2K compliant.
Do not disable this clock via the Chip Control Register (bit-11 at CD:CCh) in
the 21554 PCI Configuration space.
The Secondary clock out from the 21554 is used by the CPU board. This
clock output is enabled at POR by an external strapping option.