Specifications

EPC-3305 Hardware Reference
48
The 443BX generates all control signals (such as ~RAS, ~CAS, ~WE, ~CS, and
~DQM) and multiplexed addresses for the SDRAM array. The address and data
flow through the 443BX for all SDRAM accesses.
PIIX4E PCI-ISA bridge
The Intel PIIX4E is a 324 pin BGA that runs on +3.3V with a reference voltage tied
to +5V for +5V signal compatibility. It dissipates a maximum of 1 W. The PIIX4E
provides support for a PCI-to-ISA bridge, an IDE controller, compatibility devices, a
dual USB controller, SMBus, a real time clock (RTC), and power management logic.
A detailed description of each of these follows.
PCI-ISA bridge
The PIIX4E is PCI 2.1 and IEEE996 compatible (ISA, AT bus). On PCI, the PIIX4E
operates as a bus master for various internal modules, such as the USB controller,
DMA controller, IDE bus master controller, distributed DMA masters, and on
behalf of ISA masters. Internal registers or cycles passed to the ISA or EIO buses
make the PIIX4E operate as a target. All internal registers are positively decoded.
The PIIX4E chip drives the ISA bus directly. The PIIX4E incorporates an ISA bus
compatible master and CPU interface, and can drive five ISA slots without external
data buffers. The ISA interface also provides byte swap logic, I/O recovery support,
wait state generation, and SYSCLK generation. There are three devices on the CPU
board connected to the ISA bus: SuperI/O, Flash ROM BIOS, and Watchdog CPLD.
IDE controller
The PIIX4E fast IDE interface supports up to four IDE devices through two
independent IDE signal channels. The IDE interface supports PIO IDE transfers up
to 14 MB/s and Bus Master IDE transfers up to 33 MB/s. It does not consume any
ISA DMA resources and integrates eight 32-bit buffers for optimal transfers.
The PIIX4E chip supports Modes 1, 2, 3, and 4 as well as Bus Master (DMA)
Modes 0, 1, and 2. There is no support for the obsolete IDE register at I/O address
0x3F7. The PIIX4E supports “Ultra DMA/33” Synchronous DMA Mode Transfers.
Only PCI Masters have access to the IDE port. ISA Bus masters cannot access the
IDE I/O port addresses. The IDE data transfer command strobes, DMA request and
grant signals, and IORDY signals interface directly to the PIIX4E chipset.
The primary IDE channel is connected to on-board Flash with an IDE interface. A
header for the secondary IDE is available on the RTM.
Compatibility devices
The PIIX4E contains three compatibility devices:
• DMA controller: The DMA controller incorporates the logic of two 82C37
DMA controllers. The DMA controller has seven independently programmable
channels. Channels [3:0] are hardwired to 8 bit, count-by-byte transfers.
Channels [7:5] are hardwired to 16-bit, count by word transfers. Any two of the
seven DMA channels can provide support for fast Type-F transfers. The DMA