Specifications

Chapter 4: Theory of operation

The BIOS initialization software copies the ROM contents into DRAM (a process

called shadowing) at addresses E0000h

–FFFFFh. The VGA BIOS is copied into

C0000h

–C7FFFh of DRAM. After copying into these areas, the BIOS write-protects

them. Subsequent writes to these areas complete successfully but do not alter the

data in DRAM.

There are two parameter blocks, each 8KB in size, used for BIOS code.

443BX host bridge

The Intel 443BX is a 492 pin BGA running on 3.3V with mixed +5V, 3.3V, and

GTL+ termination voltages. It dissipates a maximum of 3W if AGP is disabled. The

443BX contains support for a CPU-to-PCI bridge, a CPU-to-AGP bridge, a DRAM/

SDRAM memory controller, and the central arbitration functions for the PCI bus.

The 443BX supports concurrent CPU, AGP, and PCI transactions to main memory.

443BX PCI bus

The Intel 443BX supports CPU-to-PCI cycles. The 443BX and the PCI CLK run at

33 MHz. When acting as a PCI target, the 443BX does not respond to the cycles

listed in the left column of Table 4-1. When acting as a bus master on behalf of the

CPU, the 443BX does not issue PCI commands for the host bus commands listed in

the right column of Table 4-1.

PCI Bus features include:

• Fully synchronous, minimum latency 33 MHz PCI bus interface

• Zero wait state CPU-to-PCI write timings (no IRDY stall)

• PCI 2.1 compliant

• Data streaming support from PCI to DRAM

• Supports five PCI bus masters in addition to the Host and PCI to ISA bridge

DRAM/SDRAM memory controller

The 443BX supports 66 MHz or 100 MHz SDRAM memory. Memory is in a

16Mx8-bit format. The CPU includes four banks of nine chips, each bank capable

of accommodating 128MB of memory with ECC. The CPU board may be

purchased with 128MB, 256MB, or 512MB of soldered-down memory.

Table 4-1. 443BX unsupported commands

PCI target Host bus

Interrupt acknowledge Deferred reply

Special cycle Branch trace message

I/O read Memory read of 16 bytes

I/O write Memory write of 16 bytes

Configuration read EA memory access

Configuration write

Dual address cycle

Reserved commands