Specifications

Chapter 4: Theory of operation
45
Memory map
The 2
32
byte physical address space seen by the Intel Pentium III occupies three
areas:
1. From 0 to 1 MB is largely defined by the IBM PC/AT architecture.
2. From 1 to 256 MB depends on how much DRAM is installed in the EPC-3305.
3. Memory addresses from the Pentium between 0 and 4 MB (0FFFFFFFh) is
mapped as follows:
1
If no BIOS extensions, ISA bus (aliased); not cacheable.
2
If no DRAM, ISA bus (aliased); not cacheable.
Interrupt usage
For details about EPC-3305 PC-compatible interrupt usage, see Appendix B,
Interrupts.
Flash boot device
A boot block Flash memory stores system start-up code for the CPU board. This is
flash-updatable BIOS containing the boot, main, and parameter blocks shown in
Figure 4-2. The Main and Parameter blocks of the BIOS are reprogrammed under
program control. Registers contained within the 443BX protect these areas from
inadvertent writes. The BIOS chip select signal asserts only when the chipset is to
write within the range of the BIOS Flash boot device. This device is 1Mbyte and is
controlled as having two pages of 512kBytes. A register in the CPLD controls
the paging.
Range Content Cacheable
0–640Kb
00000000–0009FFFF First 640 KB of DRAM
(DOS memory)
Ye s
640Kb–1MB
000A0000–000BFFFF VGA video DRAM, mapped
to the Video Module
No
000C0000–000CBFFF Write-protected DRAM
containing shadowed video
BIOS (48 KB)
Ye s
000D0000–000DFFFF BIOS extensions
Ye s
1
000E0000–000FFFFF System BIOS shadow Yes
1MB–512MB 00100000
–0FFFFFFF DRAM (511 MB)
Ye s
2
512MB–top
1MB
10000000–FFEFFFFF ISA bus (aliased) No
Top 512Kb
FFF80000–FFFFFFFF Flash memory No