Specifications

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µ EPC-2 HARDWARE REFERENCE
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5. Theory of Operation
This chapter specifies other information about the operation of the EPC-2 that
might be useful to the system designer.
Processor, Coprocessor, Memory
The processor is an Intel 80386. The optional .i.coprocessor; is an 80387. The
387 is a factory-installed option.
The processor board contains eight SIMM sockets. The factory-installed .i.DRAM
options; are 2, 4, 8, and 16 MB. The DRAM has byte-wide .i.parity;.
ROM and ROM Shadowing
EPC-2 contains a 27011 page-mode EPROM. The .i.EPROM; is mapped into the top of
the processor's 32-bit address space, and also just below the 16 MB boundary for
PC/AT compatibility. Alternate pages of the EPROM are accessed by using the
page register in the EPROM chip. The EPROM contains the PC BIOS, VGA BIOS, SCSI
disk BIOS, selftest program, and the setup screen program.
.i.ROM shadowing;For best possible performance, the BIOS initialization software
copies the ROM contents into DRAM (called shadowing). DRAM at addresses 0Fxxxxh
holds all but the VGA BIOS. DRAM at addresses 0Cxxxxh holds the VGA BIOS
(beginning at 0C0000h). The BIOS write-protects these areas of memory.
GPIB Controller
The .i.GPIB controller; in the EPC-2 is fully software compatible with the
National Instruments GPIB-PCII interface card. Because it is built into the
EPC-2, its configuration is static. Specifically, it uses interrupt IRQ5, DMA
channel 1, and I/O base address 2B8.
Battery
The .i.battery; powers the .i.CMOS RAM; and .i.TOD clock; when system power is
not present. In older versions of the EPC-2, the battery is mounted on the
circuit board and is not user replaceable. In newer versions, the battery is
mounted on a velcro strip and connected to the circuit board via two wires to a
four-pin keyed header. This battery may be replaced in the field using RadiSys
part number 07-0018. Do this in a static-free environment and avoid touching
the circuit board.
Interrupts and DMA Channels
.i.interrupt mapping;The assignment of interrupts is shown in the following
table:
NMI DRAM parity error, I/O channel check
IRQ0 timer
IRQ1 keyboard
IRQ3 .i.COM2; serial port
IRQ4 .i.COM1; serial port
IRQ5 .i.GPIB controller;
IRQ6 .i.floppy disk controller;
IRQ7 .i.LPT1; parallel port
IRQ8 clock
IRQ9 .i.VGA controller;
IRQ10 VXI interrupt/event
IRQ11 unassigned
IRQ12 .i.SCSI controller; (revised EPC-2)
unassigned (older EPC-2s)
IRQ13 coprocessor
IRQ14 .i.IDE; disk (revised EPC-2)
SCSI controller (older EPC-2s)
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