Specifications

The EPC-2 contains byte ordering hardware to allow programs to view VMEbus mem-
ory in either byte order. The order is selected by bit BORD in the .i.VME
modifier register;.
When .i.little endian; is selected, bytes pass straight through from the 386's
"byte lanes" to the VMEbus byte lanes (or vice versa on a read). That is, data
lines 0-7 on the 386 connect to data lines 0-7 on the VMEbus (also called VME
BYTE(0)), 8-15 to 8-15, 16-23 to 16-23, and 24-31 to 24-31.
When .i.big endian; is selected, the bytes are swapped between the 386 and VME.
For a D16 access, 386 data lines 0-7 connect to data lines 8-15 on VME, and 386
data lines 8-15 connect to 0-7 on VME. For D32 accesses, the "outer two" and
"inner two" bytes are swapped (i.e., 386 data lines 0-7 connect to VME data
lines 24-31, 8-15 to 16-23, 16-23 to 8-15, and 24-31 to 0-7).
Byte swapping applies only to EPC-2 initiated (master) accesses; it does not
apply to .i.slave; accesses (accesses from other VMEbus masters to the EPC-2's
DRAM).
The EPConnect .i.Bus Manager; software provides functions for swapping byte
ordering during memory-copy operations.
Read-Modify-Write Operations
.i.RMW cycle;Read-modify-write cycle;VXIbus RMW (read-modify-write) cycles can
be performed through use of the 386's .i.LOCK instruction prefix; with certain
instructions. All of these instructions perform a read followed by a write.
When such a read occurs that is mapped to the VXIbus, the EPC-2 treats it as the
start of a VXI RMW cycle. The next VME access from the 386 is treated as the
write that terminates the RMW cycle. For this reason, RMW accesses that cross a
32-bit boundary will not behave as expected (because the 386 issues two read
accesses).
Slave Accesses from the VMEbus
.i.slave;When SLE in the status/control register is set, the EPC-2 will respond
to accesses in a 16 MB range of the A32 space. All types of VME accesses
(reads, writes, and read-modify-writes of all lengths) are supported, except for
.i.block transfer cycles;. The .i.address modifier; can specify supervisory,
nonprivileged, program, or data.
When such an access is fielded by the EPC-2, the EPC-2's A24 or A32 base address
is effectively subtracted from the VMEbus address value, and the result is
treated, with several exceptions, as if the access came from the 386. The
mapping of VXI slave-access addresses to addresses as seen by the 386 is shown
in the following table.
VXI address range Mapped to this local
address in the EPC-2
zz000000 zz09FFFF 00000000 0009FFFF
zz0A0000 zz0BFFFF 00100000 0011FFFF
zz0C0000 zz0CFFFF 000C0000 000CFFFF
zz0D0000 zz0EFFFF 00120000 0013FFFF
zz0F0000 zz0FFFFF 000F0000 000FFFFF
zz100000 zz13FFFF hidden memory
zz140000 zzFDFFFF 00140000 00FDFFFF
The .i.hidden memory; is DRAM in the EPC-2 that, because of the memory mapping,
is accessible by VXI slave accesses but is not directly accessible from the 386.
Also, note that slave accesses can reach two areas that are write-protected from
the 386. These areas are not write-protected from slave accesses.
Self Accesses Across the VMEbus
.i.self accesses;Since the EPC-2's DRAM can be mapped into the VXI A32 address
space, the EPC-2 can access its DRAM in an alternate way: by generating VXI
accesses to the appropriate addresses. This can be of use in multiple-processor
systems where some of the EPC-2's DRAM is used as shared global memory; it means
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com