Specifications

send the message; otherwise the sender must reread VARE until this condition is
true. For 16-bit messages, the sender writes into .i.VML;. For 32-bit
messages, the sender must write into .i.VMH; before writing into VML.
The bits RRDY, WRDY, ABMH, and MLCK in the .i.response register; are altered by
hardware-detected conditions. A read from VML clears RRDY. A write into all or
the lower 8 bits of VML clears WRDY. A read or write to all or the lower 8 bits
of VMH clears ABMH. A read of VARE clears MLCK if WRDY is set.
.i.VME A31-24 Address Register; (.i.BWA;)
VMEbus Address bits 31-24
8150
This register is one of several that supply the VXIbus address bits when the
EPC-2 makes an access in its ".i.E page;." This register supplies address bits
A31-A24.
.i.VME Modifier Register; (.i.BWM;)
VME WA23-22 BORD IACK AM5 AM4 AM2 AM1
8151
.i.VMEbus address modifier;.i.address modifier;This register is also used when
the EPC-2 makes an access through its .i.E page; to the VXIbus. Bits 7 and 6
provide VXI address bits A23 and A22, respectively. Bits 3-0 define the value
placed on the associated VXI address-modifier lines. Register bits are not
defined for the address-modifier AM3 and AM0 lines since, for all defined
address-modifier values in the VMEbus specification, AM3 is 1 and AM0 is the in-
verse of AM1. Therefore these two bit values are generated by hardware.
BORD .i.byte ordering;Byte order. This bit controls the ordering of data bytes
for D16 and D32 VXIbus accesses. If 0, the bytes are transmitted in .i.little
endian; (Intel) order; if 1, byte-swapping hardware transmits the bytes in
.i.big endian; (Motorola) order. Refer to a subsequent section in this chapter
for more information on byte ordering.
IACK This bit, when set, is used to define the VXIbus access as an .i.interrupt
acknowledge; cycle. The interrupt being acknowledged must be encoded by soft-
ware as a value on address lines A1-A3.
.i.VME Interrupt State Register; (.i.BIS;)
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR
8152
This read-only register defines the state of the VXI and message interrupts.
IRQx If clear (0), the associated VXI interrupt line is asserted.
MSGR If clear (0), a .i.message interrupt; is being signalled. MSGR is clear
if both of bits RRDY and WRDY in the .i.response register; are clear..i.MSGR
interrupt;
.i.VME Interrupt Enable Register; (.i.BIE;)
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR
8153
This is a mask of the interrupt conditions in the interrupt state register. A 1
denotes that the corresponding interrupt is enabled. If any bit in this
register is a 1 and the corresponding bit in the interrupt state register is a
0, the EPC-2 .i.IRQ10 interrupt; is asserted. Software may then examine the
interrupt and event state registers to determine the cause.
.i.VME Event State Register; (.i.BES;)
1 1 1 SIGR WDT ACFA BERR SYSF
8154
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