Specifications

MLCK This EPC-2 specific bit is used for synchronization of messages from
multiple senders, something not provided for in the VXI specification. If 1,
the .i.message register; can be locked for the sending of a message. If 0, the
message register has been .i.lock;ed.
WRCP This EPC-2 specific bit is a read-only copy of the WRDY bit.
FSIG Defined only when SIG=1, in which case FSIG is the number (0 or 1) of the
register in the FIFO holding the earliest signal.
LSIG Defined only when SIG=1, in which case LSIG is the number (0 or 1) of the
register in the FIFO holding the most recent signal.
FSIG and LSIG have no utility to software. They exist as read-only bits for
tests of the EPC-2 during manufacture.
Message High Register (.i.VMH;)
814C
814D
.i.message high register;This register is an extension of the VML register for
32-bit .i.longword serial messages;. An access to this register in the A16
space on the VXIbus clears flag ABMH in the .i.response register;.
Message Low Register (.i.VML;)
814E
814F
.i.message low register;This register is typically used as an incoming message
register for .i.word-serial messages;; the sender does D16 writes into it from
the VXIbus.
Shared Memory Pointer Register (.i.VSH;,.i.VSL;)
14
16
.i.shared memory pointer;These registers form a 32-bit address register for the
optional shared-memory protocol. The upper 16 bits (VSH) are not a physically
distinct register; they are the same as the .i.VSO; register. Writing the upper
8 bits of VSH has no effect; writing the lower 8 bits of VSH changes the lower 8
bits of VSO (and vice versa).
.i.Alternate Response Register; (.i.VARE;)
LOCK 1 ABMH SIG MLCK WRCP FSIG LSIG
18
1 1 1 1 1 1 1 1
19
.i.alternate response register;The upper half of this register is 1111 1111 and
the lower half is a read-only copy of the lower half of the .i.VRE; .i.response
register;. This register is associated with multiple senders of messages to the
EPC-2 and the MLCK bit; reading this register performs a test-and-set operation
on MLCK if WRDY is set.
The protocol for synchronization of multiple senders of messages is as follows.
A sender must first read VARE. If both WRDY and MLCK are set, the sender can
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