Specifications

named EXTE. Its implementation hasn't changed, but it was renamed to correspond
to the renaming of the bit in revision 1.3 of the VXIbus specification.
PASS If set (1), the EPC-2 has completed its .i.selftest; successfully. If
this bit is clear, the .i.Test LED; on the EPC-2 front panel is lit.
NOSF .i.SYSFAIL inhibit;. If set, the EPC-2 cannot assert the VXI SYSFAIL
line.
RSTP Reset EPC. Setting this bit will .i.reset; the EPC-2.
.i.Slave Offset Register; (.i.VSO;)
8146
0 0 0 1 1 SLAVE BASE
8147
If SLE is set, the value in port 8147 defines the base address of the EPC-2's
memory in the VXIbus A32 address space. This register can hold the values 18-
1F, which correspond to the base addresses 18000000-1F000000.
The value in the lower part of this register (port 8146) is read-only from the
VXIbus. See the definition of the VSH register for explanation.
.i.Protocol/Signal Register; (.i.VPR;)
1 1 1 1 1 1 1 1
8148
0 0 0 1 1 0 1 1
8149
The .i.protocol register; (the read value) defines the EPC-2 as being a
.i.servant; and .i.commander;, having a .i.signal register;, being a bus master
and an interrupter, providing the shared-memory protocol, and not providing
.i.fast handshake mode;.
When written to from the VXIbus, this register is the .i.signal register;. The
value written enters the signal FIFO (two deep) or returns a bus error
(.i.BERR;) if the FIFO is already full.
.i.Response Register; (.i.VRE;)
LOCK 1 ABMH SIG MLCK WRCP FSIG LSIG
814A
0 1 DOR DIR ERR RRDY WRDY 1
814B
This register contains some VXI-defined state bits associated with message
handling, and several EPC-2 dependent bits.
DOR RAM bit available to software. Initialized to 0.
DIR RAM bit available to software. Initialized to 0.
ERR RAM bit available to software. Initialized to 1.
RRDY .i.Read ready;. A 1 denotes that the message registers contain outgoing
data to be read by another device. RRDY is cleared when the .i.message low
register; is read.
WRDY .i.Write ready;. If set, the message registers are armed for an incoming
message. When a write occurs into the .i.message low register;message-low reg-
ister, WRDY is cleared and the .i.MSGR interrupt; condition is asserted.
LOCK RAM bit available to software. Initialized to 1.
ABMH This EPC-2 specific bit is cleared when the .i.message high register; is
read or written from the VXIbus. It serves as a .i.location monitor; for
determining whether a message is 16 or 32 bits in length.
SIG If this EPC-2 specific bit is 0, the .i.signal register FIFO; is empty.
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