Specifications

these registers. Bit 7 of this register is used as VME address bit 21, bit 6 as
VME address bit 20, ..., and bit 0 as VME address bit 14.
Bits 14-15 of the 386's address select among these four registers. Thus the
register at 8130 is associated with the address range 0E0000-0E3FFF, the one at
8132 with 0E4000-0E7FFF, and so on. The suggested usage is to maintain the two
low-order bits of these registers as 00, 01, 10, and 11, respectively. This
makes the E page one contiguous 64 KB window onto the VME/VXI data transfer bus.
.i.ID Register; (.i.VID;)
1 1 1 0 1 1 0 0
8140
1 0 0 1 1 1 1 1
8141
This register defines the EPC-2 as a .i.message-based device; that is mapped
into the A16/A32 address spaces with the manufacturer being Radix MicroSystems
(.i.manufacturer code; 4076).
Since the EPC-2 is a .i.DC device; (a device without a static ULA, but a ULA
that can be assigned dynamically by the .i.resource manager;), an initial write
into this register from the VXIbus assigns a ULA to the EPC-2.
.i.Device Type Register; (.i.VDT;)
1 1 1 1 1 1 1 1
8142
0 1 1 1 0 0 0 S
8143
This read-only register denotes that the EPC-2 responds to a 16 MB range in the
.i.A32; space and has a .i.model code; of 255 (S=0) or 511 (S=1). S is
controlled by the SLOT 0 FUNCTIONS parameter on the BIOS setup screen. S=0
(model code 255) means that the EPC-2 is configured as a slot-0 controller.
.i.Status/Control Register; (.i.VSC;)
SRIE POSR SYSC 1 READY PASS NOSF RSTP
8144
SLE MODID SYSR 1 1 1 1 1
8145
This register contains VXI specified bits and EPC-2 device-dependent bits.
SLE .i.Slave enable;. If set (1), the EPC-2 will respond to certain A32
accesses from the VXI data-transfer bus.
.i.MODID; If clear (0), it denotes that the EPC-2's MODID pin is being
asserted.
SYSR SYSRESET. The EPC-2 asserts the VXI .i.SYSRESET; line while this bit is
1. When using this bit, it is software's responsibility to ensure that the
VXI/VME specified minimum assertion time of SYSRESET is met.
SRIE .i.SYSRESET input enable;. If set, assertion of VXI SYSRESET generates a
reset of the EPC-2. One use of this bit is having software reset the VXI system
(via bit SYSR) without resetting the EPC-2.
POSR This specifies the value of the low-order bit of the .i.nonvolatile option
register;, a shift register in the EPC-2 also known as the .i.POS register;.
SYSC This is an indicator of whether the VXI .i.SYSCLK; signal is functioning.
After SYSC is cleared by software, four SYSCLK rising edges will cause SYSC to
be set.
READY This RAM bit, if set while PASS=1, denotes that the EPC-2 is ready to ac-
cept operational commands. In earlier versions of this manual, this bit was
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